The device performance limit of in-plane monolayer VTe2/WTe2 heterojunction-based field-effect transistors

Abstract

To overcome the scaling restriction on silicon-based field-effect transistors (FETs), two-dimensional (2D) transition metal dichalcogenides (TMDs) have been strongly proposed as alternative materials. To explore the device performance limit of TMD-based FETs, in this work, the ab initio quantum transport approach is utilized to study the transport properties of monolayer VTe₂/WTe₂ heterojunction-based FETs possessing double gates (DGs) with a 5 nm gate length (L_g). Our theoretical simulations demonstrate that the DG–cold–source VTe₂/WTe₂ FETs with a 5 nm L_g and 2 or 3 nm proper underlap (U_L) meet the basic requirements of the on-state current (I_on), power dissipation (PDP), and delay time (τ) for the 2028 needs of the International Technology Roadmap for Semiconductor (ITRS) 2013, which ensures their high-performance and low-power-dissipation device applications. Moreover, the DG-cold-source VTe₂/WTe₂-based FETs with a 3 nm L_g and 2 or 3 nm U_L meet the high-performance requirements of I_on, τ, and PDP for the 2028 needs of ITRS 2013. Additionally, by further considering the negative capacitance technology in devices, the parameters τ, I_on, and PDP of the VTe₂/WTe₂-based FETs with a 1 nm L_g and 3 nm U_L meet well with the 2028 needs for ITRS 2013 towards high-performance device applications. Our theoretical results uncover that the 2D DG-cold-source VTe₂/WTe₂ FETs can be used as a new kind of promising material candidate to drive the scaling of Moore's law down to 1 nm.